1. Technical Field
Various embodiments of the present invention relate to a semiconductor integrated circuit apparatus, and more particularly, to a semiconductor integrated circuit apparatus having a configuration that may enable reduction in its plane area.
2. Related Art
In general, a NAND flash memory stores charge in a floating gate using a tunneling phenomenon or performs a programming or erase operation by discharging the charge stored in the floating gate to a channel.
The programming and erase operations are suitable for a non-volatile memory because they satisfy for the required condition for preserving stored data. Since a flash memory has high integration, low power consumption, and high endurance against external impact, it has been extensively used as an auxiliary storage device of a mobile device and various other applications.
The flash memories can be classified into a NAND type flash memory and a NOR type flash memory. Currently, due to consideration of integration density, among other things, the NAND type flash memory is mainly used.
The NAND type flash memory includes a plurality of memory cell blocks having a drain select transistor, a source select transistor, and a cell string connected therebetween. The cell string represents an element in which 16 or 32 MOS transistors are serially connected to one another. Such cell blocks form a group to achieve a memory cell array.
FIG. 1 is a schematic circuit diagram of a conventional flash memory apparatus. The flash memory apparatus 10 may include a plurality of memory cell blocks 20, a plurality of word line selection units 30, and a plurality of block selection units 40. Each memory cell block 20 may be divided into a plurality of cell strings ST and a plurality of pages P.
Each word line selection unit 30 includes a plurality of switching transistors, each of which corresponds to the respective one of the pages P. The switching transistors provide signals of a plurality of global word lines GWL<0:31> to a plurality of local word lines LWL<0:31>, respectively, in response to output signals of the block selection units 40 (i.e., block select word line signals BLSWL for driving the word line selection units 30).
One block selection unit 40 is provided for each memory cell block 20. Each block selection unit 40 generates the block select word line signal BLSWL to drive each word line selection unit 30.
The plurality of global word lines GWL<0:31> are provided between the block selection units 40 and the word line selection units 30. The plurality of global word lines GWL<0:31> are shared by the plurality of word line selection units 30. With such a configuration, a corresponding block selection unit 40 is driven, so that the signals of the plurality of global word lines GWL<0:31> are transmitted to a corresponding memory cell block 20.
However, since the respective switching transistors constituting the word line selection units 30 should switch a high voltage when reading, programming, and erasing the memory cell blocks 20, the switching transistors are fabricated in a relatively wide area. Therefore, it is difficult to reduce the area of the flash memory apparatus.